Typical integrated circuits (ICs) have large numbers of elements that are synchronized to a system clock. Different clock distribution methods can be used to distribute the system clock across the chip to these elements. However, as the clock signal propagates through the clock distribution structure, issues such as process, voltage and temperature variations can affect the delay of the clock signal. In order to ensure proper synchronous behavior, the clock signals arriving at these elements may need to be aligned to the system clock. Delay locked loops (DLLs) are typically used to align the distributed clock signals to a reference clock prior to their use by the synchronous elements.